Quantum Blockchain Technologies PLC (AIM:QBT) earlier this week filed a patent application for its AI Oracle technology.
The company said the Oracle enhances the efficiency of ASIC chips used in Bitcoin mining by optimizing the SHA process.
The AI Oracle uses an advanced learning algorithm, described by Chairman and CEO Francesco Gardin as “Method C,” to analyse vast quantities of data.
It makes real-time decisions about whether an input is likely to generate a winning hash. Gardin noted that the technology improves efficiency while maintaining the chip’s clock speed and avoiding production-line inefficiencies, such as “bubble problems.”
Chief executive Francesco Gardin joined the Proactive studio to talk through the developments. Here’s what was said …
Proactive: Hello, you're watching Proactive. I'm joined by Quantum Blockchain Technologies chairman and CEO Francesco Gardin. Francesco, very good to speak with you. You filed a patent application for AI Oracle. Tell us what this patent covers.
Francesco Gardin: Good morning, Stephen. It’s always a pleasure being with you.
Yes, indeed. We filed this patent; it was a very tough technical job, which lasted several months. And then, as usual with patents, you have to go from the invention, the concept, to turn it into a legal document, which is not always a straightforward exercise.
So, as you will remember, we have one of our three methods, which is Method C. This method trains by looking at billions and trillions of algorithm outputs and inputs.
Once this learning method has completed its job, it produces an Oracle.
Basically, the Oracle decides in real time whether an input to SHA, which is the double SHA, has a chance to generate the winning hash or not. Now, while this might seem simple, in reality, it’s not.
We are dealing with an ASIC chip, which has a very simple architecture because it has many lanes of SHA at the same speed (the chip’s clock). Like a production line, each lane processes an input.
If you have an Oracle on the chip, you must ensure none of these clocks are missed, or you encounter what we call the "bubble problem."
On a production line, if a part is missing, it causes a bubble that cannot be processed.
A) We have to make sure the Oracle is fast enough to deal with a thousand lanes and not miss a single one.
B) The implementation of the Oracle must be extremely efficient. In fact, it takes between 1 and 4% of the silicon cost. This is the main objective, and it’s not obvious at all. That’s why we protected it with a patent.
We are now in a position to disclose this application to third parties. It’s important to note that our patent attorney was very clear—until we filed the patent, we couldn’t discuss the implementation, as it would compromise its validity.
Now that it’s in place, we’re ready to commercialize and approach potential partners to license this technology.
Proactive: Francesco, what do the initial tests tell you about AI Oracle?
Francesco Gardin: You cannot produce an ASIC chip directly - it’s too expensive. It costs 2 million just for a prototype and another 15 – 16 million for production.
Instead, we developed it on an FPGA, which is a programmable hardware chip. This gives a clear indication of feasibility and efficiency.
Our results, using metrics like PPA (Power, Performance, and Area), show the Oracle performs efficiently. The system is live and performs as expected.
Proactive: Are you encouraged by what you've seen so far, Francesco?
Francesco Gardin: Absolutely. Filing the patent was a prerequisite to tell the world what we can do. Now we can focus on improving the Oracle’s performance.
We’ve moved it from lab testing to an actual working system in real time.
We can now demo two FPGAs—one with the Oracle and one without it—to prove that the Oracle enhances performance.
Essentially, it reduces unnecessary computations in the double SHA process, which is our method’s key advantage.
Proactive: So, what are the next steps, then, Francesco?
Francesco Gardin: The next step is further improving Oracle’s performance by retraining our Model C learning algorithm.
Once we are satisfied with the results, we’ll provide real-time demos linked to a pool.
Since we are using an FPGA with seven lanes, it cannot compete with an ASIC’s 1,000 lanes. But what really matters is the principle.
If it works at this level, it can be extended to ASIC.
ASIC manufacturers will acquire our IP under a licensing model, similar to how ARM operates. ARM doesn’t manufacture chips; it licenses its IP.
We plan to approach manufacturers soon, and Jose Rios, a key team member with experience in block-scale chips, will facilitate introductions and demonstrations.
Proactive: Francesco, I hope you’ll keep us updated on any progress. Thank you very much for the update today.
Francesco Gardin: Thank you, Stephen. Always a pleasure.